For a configuration of an arithmetic unit of a semiconductor integrated circuit and a peripheral circuit thereof, there has been a conventional arithmetic circuit having a circuit configuration as shown in FIG. 1. According to this arithmetic circuit, one input data DA of an adder 72 is inputted to one input terminal of an AND gate 71 while the other input data DB of the adder 72 is inputted to one input terminal of an AND gate 70. A signal ENB representing that operation data is valid is inputted to the other input terminals of the AND gates 70 and 71, wherein when the signal ENB is logical “H” level (valid), the input data DA, DB pass through the AND gates 70, 71 and they are inputted to the adder 72 while when the input data DA, DB are logical “L” level (invalid), input signals SA, SB of the adder 72 are rendered “L” level to allow the adder 72 inoperative, thereby enhancing low consumption of the arithmetic circuit (see timing chart of FIG. 2).
However, according to the conventional arithmetic circuit, gate circuits such as AND circuits and so forth are provided at the pre-stage of the arithmetic unit, a delay of data path from the input of data to the holding of the data in a register 74 becomes large, arising a problem to make it difficult to operate at high speed.